The recent advances in very deep sub-micron (VDSM) integrated circuits (ICs) have brought new challenges in the design closure methodologies of integrated systems. The use of more advanced process nodes, more functionality consolidation into a single die area, and increasing complexity due to, for example, hard IP usage have resulted in increased scale and complexity of electronic circuits. This also poses challenges on design closure that closes on an electronic design which takes a netlist of the electronic design and closes on the design to bring the electronic design to tapeout-readiness. For example, the use of memory has also increased due to the increased scale and complexity of electronic circuit designs and the incorporation of more functionality into a single die.
One approach to tackle the memory utilization problem is to use a hierarchical design methodology. A hierarchical electronic design includes a top level that is the highest hierarchical level in the hierarchy of the electronic design. A typical hierarchical electronic design methodology includes the steps of partitioning the electronic design into one or more blocks or sub-chips (hereinafter block), designing the top level and each block separately, assembling the block(s) into the top level, and trying to close on the entire design including interface timing. Conventional hierarchical approaches use black boxes or macro libraries to represent some or all of the blocks. Some approaches uses the interface logic model (ILM) to represent one or more blocks belonging to the top level and thus do not allow changes inside one or more of the blocks. Some other approaches uses active logic reduction technology (ART) that requires a full netlist, and thus the memory reduction is limited to reduced timing graph.
Thus, there exists a need for implementing full-chip optimization with reduced physical design data.